Communication channel calibration for drift conditions

ABSTRACT

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of co-pending U.S. patentapplication Ser. No. 17/386111, filed Jul. 27, 2021, entitledCOMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS, whichapplication is a continuation of co-pending U.S. patent application Ser.No. 16/861164, filed Apr. 28, 2020 (now U.S. Pat. No. 11,108,510),entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS, whichapplication is a continuation of application Ser. No. 16/378084, filedApr. 8, 2019, entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFTCONDITIONS (now U.S. Pat. No. 10,673,582), which application is acontinuation of application Ser. No. 15/498031, filed Apr. 26, 2017,entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS (nowU.S. Pat. No. 10,305,674), which application is a continuation ofapplication Ser. No. 14/695597, filed Apr. 24, 2015, entitledCOMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS (now U.S. Pat.No. 9,667,406), which application is a continuation of application Ser.No. 14/201778, filed 7 Mar. 2014, entitled COMMUNICATION CHANNELCALIBRATION FOR DRIFT CONDITIONS (now U.S. Pat. No. 9,042,504), whichapplication is a continuation of application Ser. No. 13/846413, filed18 Mar. 2013, entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFTCONDITIONS (now U.S. Pat. No. 8,693,556), which application is acontinuation of application Ser. No. 13/409,534, filed 1 Mar. 2012,entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS (nowU.S. Pat. No. 8,422,568), which application is a continuation ofapplication Ser. No. 11/754,102, filed 25 May 2007, entitledCOMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS (now U.S. Pat.No. 8,144,792), which application is a continuation of application Ser.No. 11/459,294, filed 21 Jul. 2006, entitled COMMUNICATION CHANNELCALIBRATION FOR DRIFT CONDITIONS (now U.S. Pat. No. 7,415,073); which isa continuation of U.S. patent application Ser. No. 10/766,765, filed 28Jan. 2004, entitled COMMUNICATION CHANNEL CALIBRATION FOR DRIFTCONDITIONS, now U.S. Pat. No. 7,095,789; which prior applications areincorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to the calibration of communicationchannel parameters in systems, including mesochronous systems, in whichtwo (or more) components communicate via an interconnection link; and tothe calibration needed to account for drift of conditions related tosuch parameters during operation of the communication channels.

Description of Related Art

In high-speed communication channels which are operated in amesochronous manner, typically a reference clock provides frequency andphase information to the two components at either end of the link. Atransmitter on one component and a receiver on another component eachconnect to the link. The transmitter and receiver operate in differentclock domains, which have an arbitrary (but fixed) phase relationship tothe reference clock. The phase relationship between transmitter andreceiver is chosen so that the propagation delay seen by a signalwavefront passing from the transmitter to the receiver will notcontribute to the timing budget when the signaling rate is determined.Instead, the signaling rate will be determined primarily by the drivewindow of the transmitter and the sample window of the receiver. Thesignaling rate will also be affected by a variety of second ordereffects. This system is clocked in a mesochronous fashion, with thecomponents locked to specific phases relative to the reference clock,and with the drive-timing-point and sample-timing-point of each linkfixed to the phase values that maximize the signaling rate.

These fixed phase values may be determined in a number of ways. Asideband link may accompany a data link (or links), permitting phaseinformation to be passed between transmitter and receiver.Alternatively, an initialization process may be invoked when the systemis first given power, and the proper phase values determined by passingcalibration information (patterns) across the actual link. Once thedrive-timing-point and sample-timing-point of each link has been fixed,the system is permitted to start normal operations.

However, during normal operation, system conditions will change. Ambienttemperature, component temperature, supply voltages, and referencevoltages will drift from their initial values. Clock frequencies maydrift due to environmental and operational factors, or be intentionallycaused to drift in spread spectrum clock systems, and the like.Typically, the frequency drift will be constrained to lie within aspecified range, and many of the circuits in the components will bedesigned to be insensitive to the drift. Nonetheless, the drift willneed to be considered when setting the upper signaling rate of a link.In general, a channel parameter may be calibrated as a function of oneor more changing operating conditions or programmed settings. In manycases, drifting parameters will be plotted in the form of atwo-dimensional Schmoo plot for analysis. Examples of programmedsettings, which might be subject of calibration, or which might causedrift in other channel parameters, include transmitter amplitude,transmitter drive strength, transmitter common-mode offset, receivervoltage reference, receiver common-mode offset, and line terminationvalues.

As the conditions drift or change, the optimal timing points of thetransmitter and receiver will change. If the timing points remain attheir original values, then margin must be added to the timing windowsto ensure reliable operation. This margin will reduce the signaling rateof the link.

It is desirable to provide techniques to compensate for the conditiondrift, and provide improvements in system and component design to permitthese techniques to be utilized.

SUMMARY OF THE INVENTION

The present invention provides a system and method for calibrating acommunication channel, which allows for optimizing timing windows andaccounting for drift of properties of the channel. A communicationchannel includes a first component having a transmitter coupled to anormal data source, and at least a second component having a receivercoupled to a normal signal destination. A communication link couples thefirst and second components, and other components on the link. Thepresent invention includes a method and system that provides forexecution of calibration cycles from time to time during normaloperation of the communication channel. A calibration cycle includesde-coupling the normal data source from the transmitter and supplying acalibration pattern in its place. The calibration pattern is transmittedon the link using the transmitter on the first component. Aftertransmitting the calibration pattern, the normal data source isre-coupled to the transmitter. The calibration pattern is received fromthe communication link using the receiver on the second component. Acalibrated value of a parameter of the communication channel isdetermined in response to the received calibration pattern. In someembodiments of the invention, the communication channel isbidirectional, so that the first component includes both a transmitterand a receiver, and second component likewise includes both atransmitter and receiver.

The communication channel transmits data using the transmitter on thefirst component and receives data using the receiver on the secondcomponent with a first parameter of the communication channel, such asone of a receive and transmit timing point for the transmissions fromthe first to the second component, set to an operation value, andreceives data using the receiver on the first component and transmitsdata using the transmitter on the second component with a secondparameter of the communication channel, such as one of a receive andtransmit timing point for the transmissions from the second to the firstcomponent, set to an operation value.

According to one embodiment of the invention, a method comprises:

-   -   storing a value of a first edge parameter and a value of a        second edge parameter, wherein an operation value of said        parameter of the communication channel is a function of the        first and second edge parameters;    -   executing a calibration cycle;    -   the calibration cycle including iteratively adjusting the value        of the first edge parameter, transmitting a calibration pattern        using the transmitter on the first component, receiving the        calibration pattern using the receiver on the second component,        and comparing the received calibration pattern with a stored        calibration pattern, to determine an updated value for the first        edge value;    -   the calibration cycle also including iteratively adjusting the        value of the second edge parameter, transmitting a calibration        pattern using the transmitter on the first component, receiving        the calibration pattern using the receiver on the second        component, and comparing the received calibration pattern with a        stored calibration pattern, to determine an updated value for        the second edge value; and    -   as a result of the calibration cycle, determining a new        operation value for the parameter based on the function of the        updated values of the first and second edge parameters.

Some embodiments of the invention comprise a calibration methodcomprising:

-   -   executing a calibration cycle including transmitting a        calibration pattern using the transmitter on the first component        and receiving the calibration pattern using the receiver on the        second component with the first parameter set to a calibration        value, and determining a calibrated value of the first parameter        in response to the received calibration pattern; and    -   prior to determining said calibrated value of said calibration        cycle, transmitting data using the transmitter on the second        component and receiving the data using the receiver on the first        component with the second parameter set to the operation value.

Methods according to some embodiments of the invention compriseexecuting calibration cycles from time to time, the calibration cyclescomprising:

-   -   de-coupling the data source from the transmitter;    -   adjusting the parameter to a calibration value;    -   supplying a calibration pattern to the transmitter;    -   transmitting the calibration pattern on the communication link        using the transmitter on the first component;    -   receiving the calibration pattern on the communication link        using the receiver on the second component;    -   re-coupling the data source to the transmitter and setting the        parameter to the operation value; and    -   determining a calibrated value of the parameter of the        communication channel in response to the received calibration        pattern, wherein said re-coupling occurs prior to said        determining.

A variety of parameters of the communication channel can be calibratedaccording to the present invention. In some embodiments, the parameterbeing calibrated is a transmit timing point for the transmitter of thefirst component. In some embodiments, the parameter being calibrated isa receive timing point for the receiver of the second component. In yetother embodiments including bidirectional links, the parameter beingcalibrated is a receive timing point for the receiver of the firstcomponent. Also, embodiments of the present invention includingbidirectional links provide for calibration of both receive timingpoints and transmit timing points for the receiver and transmitterrespectively of the first component.

In some embodiments that include bidirectional links, calibration cyclesare executed which include a step of storing received calibrationpatterns on the second component, and retransmitting such calibrationpatterns back to logic on the first component for use in calibratingreceive or transmit timing points in the first component. In theseembodiments, the second component provides storage for holding thereceived calibration patterns for a time period long enough to allow thefirst component to complete transmission of a complete calibrationpattern, or at least a complete segment of a calibration pattern. Thestorage can be embodied by special-purpose memory coupled with thereceiver on the second component, or it can be provided by management ofmemory space used by the normal destination on the second component. Forexample, the second component comprises an integrated circuit memorydevice in some embodiments, where the memory device includes addressablememory space. The storage provided for use by the calibration cycles isallocated from addressable memory space in the memory device in theseembodiments. In yet other embodiments, where the second componentincludes latch type sense amplifiers associated with memory on thecomponent, calibration patterns may be stored in the latch type senseamplifiers while decoupling the sense amplifiers from the normallyaddressable memory space. In yet other embodiments, in which the secondcomponent comprises an integrated circuit memory having addressablememory space within a memory array, a segment of the memory arrayoutside of the normally addressable memory space is allocated for use bythe calibration cycles.

In yet other embodiments, utilization of memory at the second componentcan be improved by providing cache memory or temporary memory on thefirst component. In such embodiments, accesses to the memory array inthe second component attempted during a calibration cycle are directedto a cache memory on the first component. In other embodiments, prior toexecution of the calibration cycle, a segment of the addressable memoryin the second component to be used for storage of the calibrationpattern is copied into temporary storage on the first component for useduring the calibration cycle.

In systems and methods according to the present invention, parameterswhich are updated by the calibration process are applied to thecommunication channel so that drift in properties of the communicationchannel can be tracked to improve reliability and increase operatingfrequency of the channel. In various embodiments of the calibrationprocess, the steps involved in calibration cycles are reordered toaccount for utilization patterns of the communication channel. For lowlatency processes, for example the step of applying the updatedparameter is delayed, so that normal transmit and receive processes canbe resumed as soon as the calibration pattern has been transmitted, andwithout waiting for computation of updated parameters. For example, theupdated parameter calculated during one calibration cycle is not appliedto the communication channel, until a next calibration cycle isexecuted. In yet another example, the calibration cycle includes a firstsegment in which calibration patterns are transmitted, and a secondsegment in which updated parameters calculated during the calibrationcycle are applied, so that the time interval between completion oftransmission of the calibration pattern and completion of thecalculation of the updated parameters is utilized for normaltransmission and receive operations.

Other aspects and advantages of the present invention can be seen onreview of the drawings, the detailed description and the claims, whichfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of two components interconnected by acommunication channel.

FIG. 2 is a timing diagram illustrating timing parameters for acommunication channel like that shown in FIG. 1 .

FIG. 3 illustrates an embodiment of the present invention where both atransmitter drive point and a receiver sample point are adjustable.

FIG. 4 illustrates an embodiment of the present invention where only areceiver sample point is adjustable.

FIG. 5 illustrates an embodiment of the present invention where only atransmitter drive point is adjustable.

FIG. 6 is a flow chart illustrating calibration steps for a transmitteron a unidirectional link for a transmitter drive point.

FIG. 7 illustrates timing for iteration steps for calibrating atransmitter drive point.

FIG. 8 is a flow chart illustrating calibration steps for a receiver ona unidirectional link for a sample point.

FIG. 9 illustrates timing for iteration steps for calibrating a receiversample point.

FIG. 10 illustrates an embodiment of the present invention wheretransmitter drive points and receiver sample points on components of abidirectional link are adjustable.

FIG. 11 illustrates an embodiment of the present invention wherereceiver sample points on components of a bidirectional link areadjustable.

FIG. 12 illustrates an embodiment of the present invention where bothcomponents have adjustable transmitter drive points.

FIG. 13 illustrates an embodiment of the present invention where atransmitter drive point and a receiver sample point of only onecomponent on a bidirectional link are adjustable.

FIG. 14 is a flow chart illustrating calibration steps for a transmitterdrive point for a bidirectional link.

FIG. 15 is a flow chart illustrating calibration steps for a receiversample point for a bidirectional link.

FIGS. 16 and FIG. 17 illustrate time intervals for operation ofcomponents on a bidirectional link during calibration using a systemlike that of FIG. 13 .

FIG. 18 illustrates a first embodiment of the invention includingstorage for calibration patterns on one component.

FIG. 19 illustrates a second embodiment of the invention includingstorage within a memory core used for storage of calibration patterns onone component sharing a bidirectional link.

FIG. 20 illustrates a third embodiment of the invention includingstorage within a memory core for storage of calibration patterns on onecomponent sharing a bidirectional link, and a cache supporting use of aregion of the memory core for this purpose.

FIG. 21 illustrates a fourth embodiment of the invention includingstorage within a memory core for storage of calibration patterns on onecomponent sharing a bidirectional link, and temporary storage supportinguse of the region of the memory core for this purpose.

FIG. 22 illustrates a fifth embodiment of the invention includingstorage within sense amplifiers, which are used for storage ofcalibration patterns during calibration on one component sharing abidirectional link.

FIG. 23 is a flow chart illustrating calibration steps for a transmitteron a unidirectional link for a transmitter drive point, with re-orderedsteps for improved throughput.

FIG. 24A and 24B are flow charts illustrating calibration steps for atransmitter drive point for a bidirectional link, with re-ordered stepsfor improved throughput.

FIG. 25 illustrates an embodiment of the present invention where atransmitter drive point and a receiver sample point of one component ona bidirectional link are adjustable with a plurality of parameter sets,and wherein the bidirectional link is coupled to a plurality of othercomponents corresponding to the plurality of parameter sets.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention isprovided with reference to the Figures.

Transmitter and Receiver Timing Parameters

FIG. 1 shows two components 10, 11 connected with an interconnectionmedium, referred to as Link 12. One has a transmitter circuit 13 whichdrives symbols (bits) on Link 12 in response to rising-edge timingevents on the internal CLKT signal 14. This series of bits forms signalDATAT. The other has a receiver circuit 15 which samples symbols (bits)on Link 12 in response to rising-edge timing events on the internal CLKRsignal 16. This series of bits forms signal DATAR. FIG. 2 illustratesthe timing parameters, including the transmit clock CLKT signal 14 ontrace 20, the transmitter signal DATAT on trace 21, the receive clockCLKR signal 16 on trace 22, and the receiver signal DATAR on trace 23.The transmitter eye 24 and the receiver eye 25 are also illustrated. Thetransmitter eye 24 is a window during which the signal DATAT istransmitted on the link. The receiver eye is a sampling window definedby the is setup time and t_(H) hold time which surround the CLKR risingedge 35, 36 and define the region in which the value of DATAR must bestable for reliable sampling. Since the valid window of the DATAT signalis larger than this setup/hold sampling window labeled receiver eye 25,the receiver has timing margin in both directions.

The DATAT and DATAR signals are related; DATAR is an attenuated,time-delayed copy of DATAT. The attenuation and time-delay occur as thesignal wavefronts propagate along the interconnection medium of Link 12.

The transmitter circuit 13 will begin driving a bit (labeled “a”) nolater than a time t_(Q,MAX) after a rising edge 30 of CLKT, and willcontinue to drive it during transmitter eye 24 until at least a timet_(V,MIN) after the next rising edge 31. t_(Q,MAX) and t_(V,MIN) are theprimary timing parameters of the transmitter circuit 13. These twovalues are specified across the full range of operating conditions andprocessing conditions of the communication channel. As a result,t_(Q,MAX) will be larger than t_(V,MIN), and the difference willrepresent the dead time or dead band 32 of the transmitter circuit 13.The transmitter dead band 32 (t_(DEAD,T)) is the portion of the bittiming window (also called bit time or bit window) that is consumed bythe transmitter circuit 13:

t _(DEAD,T) =t _(Q,MAX) −t _(V,MIN)

The receiver circuit 15 will sample a bit (labeled “a”) during thereceiver eye 25 no earlier than a time t_(S,MIN) before a rising edge 35of CLKR, and no later than a time t_(H,MIN) after the rising edge 35.t_(S,MIN) and t_(H,MIN) are the primary timing parameters of thereceiver circuit. These two values are specified across the full rangeof operating conditions and processing conditions of the circuit. Thesum of t_(S,MIN) and t_(H,MIN) will represent the dead time or dead band37, 38 of the receiver. The receiver dead band 37, 38 (t_(DEAD,R)) isthe portion of the bit timing window (also called bit time or bitwindow) that is consumed by the receiver circuit:

t _(DEAD,R) =t _(S,MIN) +t _(H,MIN)

In this example, the bit timing window (receiver eye 25) is onet_(CYCLE) minus the t_(DEAD,T) and t_(DEAD,R) values, each of which isabout ⅓ of one t_(CYCLE) in this example.

Unidirectional Link Alternatives

FIG. 3 shows two components 100 (transmit component) and 101 (receivecomponent) connected with an interconnection medium referred to as Link102. The link is assumed to carry signals in one direction only(unidirectional), so one component 100 has a transmitter circuit 103coupled to a data source 110 labeled “normal path,” and one component101 has a receiver circuit 104 coupled to a destination 111 labeled“normal path”. There are additional circuits present to permit periodicadjustment of the drive point and sample point in between periods ofnormal system operation. These adjustments compensate for changes in thesystem operating conditions.

The transmitter component includes a block 105 labeled “pattern”, whichcan consist of pattern storage or pattern generation circuitry, andwhich is used as a source of transmit calibration patterns. Amultiplexer block 106 labeled “mux,” implemented for example using alogical layer (by which the normal data path may act as a source ofcalibration patterns and, for example, a virtual switch is implementedby time multiplexing normal data and calibration patterns) or physicallayer switch, enables the transmit calibration pattern set to be drivenonto the link by the transmitter circuit. The transmitter drive pointcan be adjusted by the block 107 labeled “adjust”. A sidebandcommunication channel 113 is shown coupled between the component 101 andthe component 100, by which the results of analysis of receivedcalibration patterns at the component 101 are supplied to the adjustblock 107 of the component 100.

The receiver component 101 includes a block 108 labeled “pattern”, whichcan consist of pattern storage or pattern generation circuitry, andwhich is used as a source of expected patterns. A block 109 labeled“compare” enables the received pattern set to be compared to theexpected pattern set, and causes an adjustment to be made to either thetransmitter or receiver. The receiver sample point can be adjusted bythe block 112 labeled “adjust”.

FIG. 4 shows two components 100, 101 connected with a unidirectionallink 102, in which components of FIG. 3 are given like referencenumerals. In the embodiment of FIG. 4 , only the receiver sample pointcan be adjusted; the transmitter drive point remains fixed during systemoperation. Thus, there is no adjust block 107 in the component 100, noris there a need for sideband communication channel 113 of FIG. 4 .

FIG. 5 shows two components 100, 101 connected with a unidirectionallink 102, in which components of FIG. 3 are given like referencenumerals. In the embodiment of FIG. 5 , only the transmitter drive pointcan be adjusted; the receiver sample point remains fixed during systemoperation. Thus, there is no adjust block 112 in the component 101 ofFIG. 5 .

In general, periodic timing calibration can be performed on all threeexamples, since timing variations due to condition drift can becompensated at either the transmitter end or the receiver end. Inpractice, it is cheaper to put the adjustment circuitry at only one endof the link, and not at both ends, so systems of FIG. 4 or 5 would havean advantage. Also, it should be noted that system of FIG. 4 does notneed to communicate information from the “compare” block 109 in thereceiver component 101 back to the transmitter component 100, and thusmight have implementation benefits over system of FIG. 5 .

Calibration Steps for Transmitter for Unidirectional Link

FIG. 6 shows the example from FIG. 5 , and also includes the stepsneeded to perform a timing calibration update.

(Step 601) Suspend normal transmit and receive operations, by completingtransactions in progress and preventing new ones from beginning, or byinterrupting transactions that are in progress.

(Step 602) Change the drive point of the transmit component from the“TX” operation value (used for normal operations) to either the “TXA” or“TXB” edge value (used for calibration operations) in the “adjust”block. The “TX” operation value may be a simple average of “TXA” and“TXB,” i.e. a center value, or it may be another function of “TXA” and“TXB,” such as a weighted average. It may be necessary to impose asettling delay at this step to allow the new drive point to becomestable.

(Step 603) Change “mux” block of the transmit component so that the“pattern” block input is enabled.

(Step 604) A pattern set is created in the “pattern” block of thetransmit component and is transmitted onto the “link” using the TXA orTXB drive point.

(Step 605) The pattern set is received in the receive component. Notethat the sample point of the receiver is fixed relative to the referenceclock of the system.

(Step 606) The received pattern set is compared in the “compare” blockto the expected pattern set produced by the “pattern” block in thereceive component. The two pattern sets will either match or not match.As a result of this comparison (and possibly other previous comparisons)a pass or fail determination will be made.

(Step 607) Adjust either the “TXA” or “TXB” edge value in the transmitcomponent as a result of the pass or fail determination. The “TX”operation value in the transmit component is also adjusted. Thisadjustment may only be made after a calibration sequence includingtransmission of two or more of calibration patterns has been executed,in order to ensure some level of repeatability.

(Step 608) Change the drive point of the transmitter from the “TXA” or“TXB” edge value (used for calibration operations) to “TX” operationvalue (used for normal operations) in the “adjust” block of the transmitcomponent. It may be necessary to impose a settling delay at this stepto allow the new drive point to become stable.

(Step 609) Change “mux” block of the transmit component so that the“normal path” input is enabled.

(Step 610) Resume normal transmit and receive operations.

Timing for Iteration Step for Transmit

FIG. 7 includes the timing waveforms used by the calibration steps ofFIG. 6 for a system like that of FIG. 5 . These timing waveforms aresimilar to those from FIG. 2 , except that the drive point is adjustedto straddle the sampling window of the receiver in order to track theedges of the valid window of the transmitter.

The “adjust” block in the transmit component maintains three values instorage: TXA, TX, and TXB. The TX value is the operation value used fornormal operation. The TXA and TXB are the “edge” values, which track theleft and right extremes of the bit window of the transmitter. Typically,the TX value is derived from the average of the TXA and TXB values, butother relationships are possible. The TXA and TXB values are maintainedby the calibration operations, which from time to time, and periodicallyin some embodiments, interrupt normal operations.

In FIG. 7 , the position of the rising edge of CLKT has an offset oft_(PHASET) relative to a fixed reference (typically a reference clockthat is distributed to all components).

When the TX value is selected (t_(PHASET(TX)) in the middle trace 701showing CLKT timing waveform) for operation, the rising edge 702 of CLKTcauses the DATAT window 703 containing the value “a” to be aligned sothat the DATAR signal (not shown but conceptually overlapping with theDATAT signal) at the receiving component is aligned with the receiverclock, successfully received, and ideally centered on the receiver eye.

When the TXA value is selected (t_(PHASE(TXA)) in the top trace 705showing CLKT timing waveform), the rising edge of CLKT is set to a timethat causes the right edges of the DATAT window 706 (containing “a”) andthe receiver setup/hold window 710 (shaded) to coincide. The is setuptime and t_(H) hold time surround the CLKR rising edge, together definethe setup/hold window 710 (not to be confused with the receiver eye ofFIG. 2 ) in which the value of DATAR must be stable for reliablesampling around a given CLKR rising edge 704. Since the DATAT window,and the resulting DATAR window, are larger than this setup/hold window710, the transmitter has timing margin. However, in the case shown ontrace 705 with the transmit clock rising edge at offset t_(PHASET(TXA)),all the timing margin is on the left side of the transmitter eye for thesetup/hold window 710, adding delay after the t_(Q) timing parameter.There is essentially no margin for the t_(V) timing parameter in thetrace 705, so that the offset defines the left edge of the calibrationwindow.

The calibration process for TXA will compare the received pattern set tothe expected pattern set, and determine if they match. If they match(pass) then the TXA value will be decremented (the T_(PHASET(TXA))offset becomes smaller shifting the transmit window 706 to the left inFIG. 7 ) or otherwise adjusted, so there is less margin for the t_(V)timing parameter relative to the receiver window 710. If they do notmatch (fail) then the TXA value will be incremented (the T_(PHASET(TXA))offset becomes larger shifting the transmit window 706 to the right inFIG. 7 , or otherwise adjusted, so there is more margin for the t_(V)timing parameter.

As mentioned earlier, the results of a sequence including transmissionof two or more calibration patterns may be accumulated before the TXAvalue is adjusted. This would improve the repeatability of thecalibration process. For example, the calibration pattern could berepeated “N” times with the number of passes accumulated in a storageelement. If all N passes match, then the TXA value is decremented. Ifany of the N passes does not match, then the TXA value is determined tohave reached the edge of the window and is incremented. In anotheralternative, after the Nth pattern, the TXA value could be incrementedif there are fewer than N/2 (or some other threshold number) passes, anddecremented if there are N/2 or more passes.

When TXA is updated, the TX value will also be updated. In this example,the TX value will updated by half the amount used to update TXA, sinceTX is the average of the TXA and TXB values. If TX has a differentrelationship to TXA and TXB, the TX update value will be different. Notethat in some embodiments, the TX value will need slightly greaterprecision than the TXA and TXB values to prevent round-off error. Inalternate embodiments, the TX value can be updated after pass/failresults of TXA and TXB values have been determined. In some cases, theseresults may cancel and produce no change to the optimal TX value. Inother cases these results may be accumulated and the accumulated resultsused to determine an appropriate adjustment of the TX setting. Accordingto this embodiment, greater precision of the TX setting relative to theTXA and TXB settings may not be required.

When the TXB value is selected (t_(PHASER(TXB)) in the bottom trace 707showing a CLKT timing waveform) for calibration, the rising edge of CLKTis set to a time that causes the left edge of the transmitter validwindow 708 (containing “a”) and the receiver setup/hold window 710(shaded) to coincide. In this case with the transmit clock rising edgeat t_(PHASER(TXB)), all the timing margin is on the right side of thetransmit window 708, providing more room than required by the t_(V)timing parameter. This means that there will be essentially no marginfor the t_(Q) timing parameter on the left side of the window 708,defining the right edge of the calibration window.

The calibration process will compare the received pattern set to theexpected pattern set, and determine if they match. If they match (pass)then the TXB value will be incremented (the offset becomes larger) orotherwise adjusted, so there is less margin for the t_(Q) timingparameter. If they do not match (fail) then the TXB value will bedecremented (the offset becomes smaller) or otherwise adjusted, so thereis more margin for the t_(Q) timing parameter.

As mentioned earlier, the results of transmission of two or morecalibration patterns may be accumulated before the TXB value isadjusted. For example, transmission of the patterns could be repeated“N” times with the number of passes accumulated in a storage element.After the Nth sequence the TXB value could be decremented if there arefewer than N/2 passes and incremented if there are N/2 or more passes.This would improve the repeatability of the calibration process.

When TXB is updated, the TX value will also be updated. In this example,the TX value will updated by half the amount used to update TXB, sinceTX is the average of the TXA and TXB values. If TX has a differentrelationship to TXA and TXB, the TX update value will be different. Notethat the TX value will need slightly greater precision than the TXA andTXB values if it is desired to prevent round-off error.

Calibration Steps for Receiver for Unidirectional Link

FIG. 8 shows the example from FIG. 4 , and also includes the stepsneeded to perform a timing calibration update. Note that only steps(Block 802), (Block 807), and (Block 808) are different relative to thesteps in FIG. 6 .

(Step 801) Suspend normal transmit and receive operations, by completingtransactions in progress and preventing new ones from beginning, or byinterrupting transactions that are in progress.

(Step 802) Change the sample point of the receive component from the“RX” operation value (used for normal operations) to either the “RXA” or“RXB” edge value (used for calibration operations) in the “adjust”block. The “RX” operation value may be a simple average of “RXA” and“RXB,” i.e. a center value, or it may be another function of “RXA” and“RXB,” such as a weighted average. It may be necessary to impose asettling delay at this step to allow the new sample point to becomestable.

(Step 803) Change “mux” block of the transmit component so that the“pattern” block input is enabled.

(Step 804) A pattern set is created in the “pattern” block of thetransmit component and is transmitted onto the “link” using the TXA orTXB drive point.

(Step 805) The pattern set is received in the receive component. Notethat the transmit point of the transmitter is fixed relative to thereference clock of the system.

(Step 806) The received pattern set is compared in the “compare” blockto the expected pattern set produced by the “pattern” block in thereceive component. The two pattern sets will either match or not match.As a result of this comparison (and possibly other previous comparisons)a pass or fail determination will be made.

(Step 807) Adjust either the “RXA” or “RXB” edge value in the receivecomponent as a result of the pass or fail determination. The “RX”operation value in the transmit component is also adjusted. Thisadjustment may only be made after two or more of these calibrationsequences have been executed, in order to ensure some level ofrepeatability.

(Step 808) Change the sample point of the receiver from the “RXA” or“RXB” edge value (used for calibration operations) to “RX” operationvalue (used for normal operations) in the “adjust” block of the receivecomponent. It may be necessary to impose a settling delay at this stepto allow the new sample point to become stable.

(Step 809) Change “mux” block of the transmit component so that the“normal path” input is enabled.

(Step 810) Resume normal transmit and receive operations. Timing forIteration Step for Receive

FIG. 9 shows includes the timing waveforms used by the receivercalibration steps of FIG. 8 for a system configured for example as shownin FIG. 4 . These timing waveforms are similar to those from FIG. 2 ,except that the sampling point is adjusted within the bit window inorder to track the edges of the window.

The “adjust” block in the receive component maintains three values instorage: RXA, RX, and RXB. The RX value is the operation value used fornormal operation. The RXA and RXB are the “edge” values, which track theleft and right extremes of the bit window. Typically, the RX value isderived from the average of the RXA and RXB values, but otherrelationships are possible. The RXA and RXB values are maintained by thecalibration operations, which periodically or otherwise from time totime interrupt normal operations.

In the timing diagrams, the position of the rising edge of CLKR has anoffset of t_(PHASER) relative to a fixed reference (not shown, typicallya reference clock that is distributed to all components). This offset isdetermined by the RXA, RX, and RXB values that are stored.

When the RX value is selected (t_(PHASER(RX)) in the middle trace 901showing a CLKR timing waveform) for use in receiving data, the risingedge 902 of CLKR is approximately centered in the receiver eye of theDATAR signal containing the value “a”. The DATAR signal is the DATATsignal transmitted at the transmitter after propagation across the link,and can be conceptually considered to be the same width as DATAT asshown in FIG. 9 . The receiver eye is shown in FIG. 2 . The t_(S) setuptime is the minimum time before the clock CLKR rising edge which must bewithin the DATAR window 903, and the t_(H) hold time is the minimum timeafter the clock CLKR rising edge that must be within the DATAR window903, together defining the setup/hold window 904 (not to be confusedwith the receiver eye of FIG. 2 ) in which the value of DATAR must bestable for reliable sampling around a given CLKR rising edge. Since thevalid window 904 of the DATAR signal is larger than this setup/holdwindow 904, the receiver has timing margin in both directions.

When the RXA value is selected (t_(PHASER(RXA)) in the top trace 905showing a CLKR timing waveform), the rising edge of CLKR isapproximately a time t_(S) later than the left edge (the earliest time)of the DATAR window 903 containing the value “a”. In this case, the CLKRrising edge is on the left edge of the receiver eye, and all the timingmargin is on the right side of the setup/hold window 904, providing moreroom than is required by the t_(H) timing parameter. This means thatthere will be essentially no margin for the t_(S) timing parameter,defining the left edge of the calibration window.

The calibration process will compare the received pattern set to theexpected pattern set, and determine if they match. If they match (pass)then the RXA value will be decremented (the offset becomes smaller) orotherwise adjusted, so there is less margin for the t_(S) timingparameter. If they do not match (fail) then the RXA value will beincremented (the offset becomes larger) or otherwise adjusted, so thereis more margin for the t_(S) timing parameter.

As mentioned earlier, the results of transmission and reception of twoor more calibration patterns may be accumulated before the RXA value isadjusted. For example, the patterns could be repeated “N” times with thenumber of passes accumulated in a storage element. After the Nthsequence the RXA value could be incremented if there are fewer than N/2passes and decremented if there are N/2 or more passes. This wouldimprove the repeatability of the calibration process.

When RXA is updated, the RX value will also be updated. In this example,the RX value will updated by half the amount used to update RXA, sinceRX is the average of the RXA and RXB values. If RX has a differentrelationship to RXA and RXB, the RX update value will be different. Notethat in some embodiments, the RX value will need slightly greaterprecision than the RXA and RXB values to prevent round-off error. Inalternate embodiments, the RX value can be updated after pass/failresults of RXA and RXB values have been determined. In some cases, theseresults may cancel and produce no change to the optimal RX value. Inother cases these results may be accumulated and the accumulated resultsused to determine an appropriate adjustment of the RX setting. Accordingto this embodiment, greater precision of the RX setting relative to theRXA and RXB settings may not be required.

When the RXB value is selected (t_(PHASER(RXB)) in the bottom trace 906showing a CLKR timing waveform), the rising edge of CLKR isapproximately a time t_(H) earlier than the right edge (the latest time)of the DATAR window 903 containing the value “a”. In this case, the CLKRrising edge is on the right edge of the receiver eye, and all the timingmargin is on the left side of the window 904, providing more room thatrequired by the t_(S) timing parameter. This means that there will beessentially no margin for the t_(H) timing parameter, defining the rightedge of the calibration window.

The calibration process will compare the received pattern set to theexpected pattern set, and determine if they match. If they match (pass)then the RXB value will be incremented (the offset becomes larger) orotherwise adjusted, so there is less margin for the t_(H) timingparameter. If they do not match (fail) then the RXB value will bedecremented (the offset becomes smaller) or otherwise adjusted, so thereis more margin for the t_(H) timing parameter.

As mentioned earlier, the results of transmission and reception of twoor more calibration patterns may be accumulated before the RXB value isadjusted. For example, the sequence could be repeated “N” times with thenumber of passes accumulated in a storage element. After the Nthsequence the RXB value could be decremented if there are fewer than N/2passes and incremented if there are N/2 or more passes. This wouldimprove the repeatability of the calibration process.

When RXB is updated, the RX value will also be updated. In this example,the RX value will updated by half the amount used to update RXB, sinceRX is the average of the RXA and RXB values. If RX has a differentrelationship to RXA and RXB, the RX update value will be different. Notethat the RX value will need slightly greater precision than the RXA andRXB values if it is desired to prevent round-off error.

Bidirectional Link Alternatives

FIG. 10 shows an example of a bidirectional link. In this case,component A (1000) and component B (1001) each contain a transmitter andreceiver connected to the link, so that information may be sent eitherfrom A to B or from B to A. The elements of the unidirectional examplein FIG. 3 is replicated (two copies) to give the bidirectional examplein FIG. 10 . FIG. 10 shows two bidirectional components 1000, 1001connected with an interconnection medium referred to as Link 1002.Normal path 1010 acts as a source of data signals for normal operationof component 1000 during transmit operations. Normal path 1031 acts as adestination of data signals for component 1000, during normal receiveoperations. Likewise, normal path 1030 acts as a source of data signalsfor normal operation of component 1001 during transmit operations.Normal path 1011 acts as a destination of data signals for component1001, during normal receive operations.

The first bidirectional component includes a block 1005 labeled“pattern”, which can consist of pattern storage or pattern generationcircuitry, and which is used as a source of transmit calibrationpatterns. A multiplexer block 1006 labeled “mux,” implemented forexample using a logical layer or physical layer switch, enables thetransmit calibration pattern set to be driven onto the link by thetransmitter circuit 1003. The transmitter drive point can be adjusted bythe block 1007 labeled “adjust”. A sideband communication channel 1013is shown coupled between the component 1001 and the component 1000, bywhich the results of analysis of received calibration patterns at thecomponent 1001 are supplied to the adjust block 1007 of the component1000. Component 1000 also has support for calibrating receiver 1024,including a block 1028 labeled “pattern”, which can consist of patternstorage or pattern generation circuitry, and which is used as a sourceof expected patterns for comparison with received patterns. A block 1029labeled “compare” enables the received pattern set to be compared to theexpected pattern set, and causes an adjustment to be made to either thetransmitter or receiver. The receiver sample point can be adjusted bythe block 1032 labeled “adjust”.

The second bidirectional component 1001 includes complementary elementssupporting transmitter 1023 and receiver 1004. For the receiveroperations, a block 1008 labeled “pattern”, which can consist of patternstorage or pattern generation circuitry, and which is used as a sourceof expected patterns. A block 1009 labeled “compare” enables thereceived pattern set to be compared to the expected pattern set, andcauses an adjustment to be made to either the transmitter or receiver.The receiver sample point can be adjusted by the block 1012 labeled“adjust”. The second bidirectional component 1001 supports transmissionoperations, with elements including a block 1025 labeled “pattern”,which can consist of pattern storage or pattern generation circuitry,and which is used as a source of transmit calibration patterns. Amultiplexer block 1026 labeled “mux,” implemented for example using alogical layer or physical layer switch, enables the transmit calibrationpattern set to be driven onto the link by the transmitter circuit 1023.The transmitter drive point can be adjusted by the block 1027 labeled“adjust”. A sideband communication channel 1033 is shown coupled betweenthe component 1000 and the component 1001, by which the results ofanalysis of received calibration patterns at the component 1000 aresupplied to the adjust block 1027 of the component 1001.

The example of FIG. 10 allows both receive sample points and bothtransmit drive points to be adjusted. However, the benefit of adjustabletiming can be realized if there is only one adjustable element in eachdirection.

The example of FIG. 11 (using the same reference numerals as FIG. 10 )shows an example in which only the receiver sample points areadjustable. Thus, elements 1007 and 1027 of FIG. 10 are not included inthis embodiment. This is equivalent to two copies of the elements ofexample in FIG. 4 .

The example of FIG. 12 (using the same reference numerals as FIG. 10 )shows an example in which only the transmitter drive points areadjustable. Thus, elements 1012 and 1032 of FIG. 10 are not included inthis embodiment. This is equivalent to two copies of the elements ofexample in FIG. 5 .

The example of FIG. 13 (using the same reference numerals as FIG. 10 )shows an example in which the receiver sample point and transmitterdrive point of the first bidirectional component 1000 are adjustable.Thus, elements 1012, 1008, 1009, 1027, 1026, 1025 are not included inthis embodiment. A storage block 1050 is added between the receiver anda “mux” block 1051. The “mux” block 1051 is used to select between anormal source of signals 1030 and the storage block 1050. Also, thecompare block 1052 is used for analysis of both transmit and receivecalibration operations, and is coupled to both the adjust block 1007 forthe transmitter, and adjust block 1032 for the receiver. Thisalternative is important because all the adjustment information can bekept within one component, eliminating the need for sideband signals forthe calibration process. If component 1001 were particularly costsensitive, this could also be a benefit, since only one of thecomponents must bear the cost of the adjustment circuitry.

Calibration Steps for Transmitter for Bidirectional Link

The calibration steps for bidirectional examples in FIGS. 10, 11 and 12can be essentially identical to the calibration steps already discussedfor unidirectional examples in FIGS. 4 and 5 . However, the asymmetry inbidirectional example of FIG. 13 will introduce some additionalcalibration steps, and will receive further discussion.

FIG. 14 shows the example from FIG. 13 , and also includes the stepsneeded to perform a timing calibration update.

(Step 1401) Suspend normal transmit and receive operations, bycompleting transactions in progress and preventing new ones frombeginning, or by interrupting transactions that are in progress.

(Step 1402) Change the drive point of the transmit component (A) fromthe “TX” operation value (used for normal operations) to either the“TXA” or “TXB” edge value (used for calibration operations) in the“adjust” block. It may be necessary to impose a settling delay at thisstep to allow the new drive point to become stable.

(Step 1403) Change “mux” block of the transmit component (A) so that the“pattern” block input is enabled.

(Step 1404) A pattern set is created in the “pattern” block of thetransmit component (A) and is transmitted onto the “link” using the TXAor TXB drive point.

(Step 1405) The pattern set is received in the receive component (B).Note that the sample point of the receiver is fixed relative to thereference clock of the system. The received pattern set is held in the“storage” block in component B.

(Step 1406) The “mux” block input connected to the “storage” block incomponent B is enabled. The pattern set is re-transmitted onto the linkby component B.

(Step 1407) The pattern set is received by component A from the link.

(Step 1408) The received pattern set is compared in the “compare” blockto the expected pattern set produced by the “pattern” block in thereceive component (A). The two pattern sets will either match or notmatch. As a result of this comparison (and possibly other previouscomparisons) a pass or fail determination will be made.

(Step 1409) Adjust either the “TXA” or “TXB” edge value in the transmitcomponent (A) as a result of the pass or fail determination. The “TX”operation value in the transmit component (A) is also adjusted. Thisadjustment may only be made after two or more of these calibrationsequences have been executed, in order to ensure some level ofrepeatability.

(Step 1410) Change the drive point of the transmitter from the “TXA” or“TXB” edge value (used for calibration operations) to “TX” operationvalue (used for normal operations) in the “adjust” block of the transmitcomponent (A). It may be necessary to impose a settling delay at thisstep to allow the new drive point to become stable.

(Step 1411) Change “mux” block of the transmit component (A) so that the“normal path” input is enabled.

(Step 1412) Resume normal transmit and receive operations.

Calibration Steps for Receiver for Bidirectional Link

The calibration steps for bidirectional examples of FIGS. 10, 11, and 12can be essentially identical to the calibration steps already discussedfor unidirectional examples of FIGS. 4 and 5 . However, the asymmetry inbidirectional example of FIG. 13 will introduce some additionalcalibration steps, and will receive further discussion.

FIG. 15 shows the example from FIG. 13 , and also includes the stepsneeded to perform a timing calibration update.

(Step 1501) Suspend normal transmit and receive operations, bycompleting transactions in progress and preventing new ones frombeginning, or by interrupting transactions that are in progress.

(Step 1502) Change the sample point of the receive component (A) fromthe “RX” operation value (used for normal operations) to either the“RXA” or “RXB” edge value (used for calibration operations) in the“adjust” block. It may be necessary to impose a settling delay at thisstep to allow the new drive point to become stable.

(Step 1503) Change “mux” block of the transmit component (A) so that the“pattern” block input is enabled.

(Step 1504) A pattern set is created in the “pattern” block of thetransmit component (A) and is transmitted onto the “link”. The normaltransmit drive point is used.

(Step 1505) The pattern set is received in the receive component (B).Note that the sample point of the receiver is fixed relative to thereference clock of the system and is not adjustable. The receivedpattern set is held in the “storage” block in component B.

(Step 1506) The “mux” block input connected to the “storage” block incomponent B is enabled. The pattern set is re-transmitted onto the linkby component B.

(Step 1507) The pattern set is received by component A from the linkusing either the RXA or RXB value to determine the receiver samplepoint.

(Step 1508) The received pattern set is compared in the “compare” blockto the expected pattern set produced by the “pattern” block in thereceive component (A). The two pattern sets will either match or notmatch. As a result of this comparison (and possibly other previouscomparisons) a pass or fail determination will be made.

(Step 1509) Adjust either the “RXA” or “RXB” edge value in the receivecomponent (A) as a result of the pass or fail determination. The “RX”operation value in the receive component (A) is also adjusted. Thisadjustment may only be made after two or more of these calibrationsequences have been executed, in order to ensure some level ofrepeatability.

(Step 1510) Change the sample point of the receiver from the “RXA” or“RXB” edge value (used for calibration operations) to “RX” operationvalue (used for normal operations) in the “adjust” block of the receivecomponent (A). It may be necessary to impose a settling delay at thisstep to allow the new sample point to become stable.

(Step 1511) Change “mux” block of the transmit component (A) so that the“normal path” input is enabled.

(Step 1512) Resume normal transmit and receive operations.

Bidirectional Link—Storage Options

The bidirectional example in FIG. 13 utilizes a storage block 1050 aspart of the calibration process. There are a number of alternativeoptions for implementing this storage, each option with its own costsand benefits.

FIG. 13 shows an option in which the storage block is implemented aspart of the interface containing the transmit and receive circuits. Thishas the benefit that the circuitry used for normal operations (the“normal path”) is not significantly impacted. The cost of this option isthat the storage block will increase the size of the interface, and willthus increase the manufacturing cost of the component 1001.

FIGS. 16 and FIG. 17 show why a storage block is needed for theimplementations of example of FIG. 13 . The storage allows the receivedpattern set in component 1001 to be held (and delayed) prior to beingre-transmitted. FIG. 16 shows a gap 1600 between the interval 1601 inwhich the pattern set is being transmitted by A (and received by B) andthe interval 1602 in which the pattern set being transmitted by B (andreceived by A). If no storage was present, there would be a relativelysmall delay between the start of each these two intervals resulting inan overlap of the intervals, as shown in FIG. 17 . In general,components on a bidirectional link are not allowed to transmitsimultaneously, so some storage will be required with the configurationof FIG. 13 to prevent this.

It is possible to design the transmitter circuits and the link so thattransmitters on both ends are enabled simultaneously. This is calledsimultaneous bidirectional signaling. In such a communication system,the storage block of configuration of FIG. 13 could be left out ofcomponent 1001. Typically, simultaneous bidirectional signaling requiresadditional signal levels to be supported. For example, if each of twotransmitters can be signaling a bit, there are four possiblecombinations of two transmitters simultaneously driving one bit each.The four combinations are {0/0, 0/1, 1/0, 1/1}. Typically the 0/1 and1/0 combinations will produce the same composite signal on the link.This requires that the transmitter circuits be additive, so that threesignal levels are produced {0, 1, 2}. The receiver circuits will need todiscriminate between these three signal levels. A final requirement ofsimultaneous bidirectional signaling is that a component must subtractthe value it is currently transmitting from the composite signal that itis currently receiving in order to detect the actual signal from theother component. When these requirements are in place, the storage blockrequirement can be dropped. This is one of the benefits of thisapproach. The cost of this approach is the extra design complexity andreduced voltage margins of simultaneous bidirectional signaling.

FIG. 18 shows option B in which the storage block is implemented fromthe storage elements 1801, 1802 that are normally present in thetransmit and receive circuits. These storage elements are typicallypresent for pipelining (delaying) the information flowing on the normalpaths. Storage elements may also be present to perform serialization anddeserialization. This would be required if the internal and externalsignal groups have different widths. For example, the external linkcould consist of a single differential wire pair carrying information atthe rate or 3200 Mb/s, and could connect to a set of eight single-endedinternal wires carrying information at the rate of 400 Mb/s. Theinformation flow is balanced (no information is lost), but storage isstill required to perform serial-to-parallel or parallel-to-serialconversion between the two sets of signals. This storage will createdelay, which can be used to offset the two pattern sets in the option ofFIG. 18 . The benefit of this approach is that no extra storage must beadded to component 1001. The cost is that the wiring necessary toconnect the receiver to a “mux” block in the transmitter may besignificant. Another cost is that the amount of storage naturallypresent in the receiver and transmitter may be relatively small,limiting the length of the pattern set which can be received andretransmitted with this approach.

FIG. 19 shows an option in which the storage block is implemented fromthe storage cells that are normally present in a memory core 1900. Inthis option, component 1001 is assumed to be a memory component. In thiscase, the storage area 1901, labeled “region”, is reserved for receivingthe pattern set from component 1000, and for retransmitting the patternset back to component 1000. This storage area may only be used by thecalibration process, and should not be used by any normal applicationprocess. If this storage area were used by an application process, it ispossible that application information could be overwritten by thepattern set information and thereby lost. The benefit of this approachis that no additional storage needs to be added to component 1001 (andno special path from receiver to transmitter). The cost of this approachis that a hole is created in the address space of the memory component.Since most memory components contain a power-of-two number of storagecells, this may create a problem with some application processes,particularly if two or more memory components must create a contiguousmemory address space (i.e. with no holes).

FIG. 20 shows an option in which the storage block is again implementedfrom the storage cells that are normally present in a memory core 1900.In this option, component B is assumed to be a memory component. In thiscase, the storage area 1901 labeled “region” is reserved for receivingthe pattern set from component 1000, and for retransmitting the patternset back to component 1000. This storage area may only be used by thecalibration process, and should not be used by any normal applicationprocess. Unlike the option in FIG. 19 , however, component 1000 adds astorage block 2001, labeled “cache”, which emulates the storagecapability of the storage area 1901 “region”. When a write is performedto the “region” of storage area 1901, it is intercepted and redirectedto the “cache” in storage 2001. Likewise, when a read is performed tothe “region” of storage area 1901, the read is intercepted andredirected, returning read data from “cache” via mux 2002. In this way,the application processes see no hole in the memory address space. Thebenefit of this option is that no additional storage needs to be addedto component 1001 (and no special path from receiver to transmitter).The cost of this approach is that a storage block 2001 “cache,” withaddress comparison logic to determine when the application is attemptingto access the region 1901, must be added to component 1000, as well asthe control logic and “mux” block 2002 needed to intercept read andwrite commands for component 1001.

FIG. 21 shows an option in which the storage block is again implementedfrom the storage cells that are normally present in a memory core 1900.In this option, component 1001 is assumed to be a memory component. Inthis case, the storage area 1901 labeled “region” is used for receivingthe pattern set from component 1000, and for retransmitting the patternset back to component 1000. This storage area 1901 may be used by boththe calibration process and by the application processes, however. Inorder to ensure that the application processes are not affected by theperiodic calibration process, a temporary storage block 2101, labeled“temp”, is provided in component 1000, along with a “mux” block 2102 foraccessing it. When a calibration process starts, the contents of“region” are read and loaded into “temp” storage block 2101. Thecalibration process steps may now be carried out using the storage area1901. When the calibration sequence has completed, the contents of“temp” storage block 2101 are accessed and written back to the “region”of storage area 1901, and the application process allowed to restart.Again, the application processes see no hole in the memory addressspace. The benefit of this option is that no additional storage needs tobe added to component 1001 (and no special path from receiver totransmitter). The cost of this approach is that a storage block 2101 andthe “mux” block 2102 must be added to component 1000. The calibrationprocess becomes longer, since a read operation must be added to thebeginning, and a write operation must be added to the end, supportingthe use of the “temp” storage block 2101.

FIG. 22 shows an option in which the storage block is implemented fromthe latching sense amplifier circuit 2201 that is present in a memorycomponent 1001. Latching sense amplifier circuit 2201 includes latchesor other storage resources associated with sense amplifiers. Most memorycomponents use such a latching sense amplifier circuit 2201 to accessand hold a row 2202 of storage cells from the memory core 1900. Readoperations are then directed to the sense amplifier which temporarilyholds the contents of the row of storage cells. Write operations aredirected to both the sense amplifier and to the row of storage cells sothat the information held by these two storage structures is consistent.When another row of storage cells is to be accessed, the sense amplifieris precharged and reloaded with this different row.

When component 1001 is a memory component with such a latching senseamplifier circuit 2201, it is possible to modify its operation to permita special mode of access for calibration. In this special mode, thesense amplifier may be written by the receiver circuit 1004 and may readto the transmitter circuit 1023 without first being loaded from a row2202 of storage cells in the memory core 1900. This permits the storageresource of the sense amplifier circuits 2201 to be used to storereceived calibration patterns, or portions of received calibrationpatterns, in region 2203 (which may include less than an entire row insome embodiments) for calibration without affecting the contents of thememory core, which would affect the interrupted application process.This second access mode would require a gating circuit 2204 between thememory core and the sense amplifier, which could be disabled during thecalibration process. There is typically such a gating circuit 2204 inmost memory components.

A benefit of this option is that no additional storage needs to be addedto component 1001 (and no special path from receiver to transmitter).The cost of this approach is that a modification must be made tocritical circuits in the core of a memory component.

Reordering of Calibration Steps to Improve Throughput

The individual steps that are shown in the calibration processesdescribed above do not necessarily have to be done in the order shown.In fact, if some reordering is done, the overhead of the calibrationprocess can be reduced, improving the effective signaling bandwidth ofthe system and reducing the worst case delay seen by latency—sensitiveoperations.

For example, in the case of the calibration process for the transmittershown in FIG. 6 , it is not necessary to perform the evaluation stepsand the update steps (compare 606 and adjust 607) in sequence as shown.Instead, the transmitter calibration process may be performed in thefollowing manner:

(Step 2301) Suspend normal transmit and receive operations, bycompleting transactions in progress and preventing new ones frombeginning, or by interrupting transactions that are in progress.

(Step 2302) Control the “adjust” logic so the transmitter uses acalibrate (TXA/TXB) drive-timing-point according to the stored resultsof the previous comparison..

(Step 2303) Control the “adjust” logic so that the pattern block iscoupled to the transmitter.

(Step 2304) A pattern sequence is read or created from the pattern blockand is transmitted onto the interconnect using the selected calibratedrive-timing-point.

(Step 2305) The pattern sequence is received using the normal (RX)sample-timing-point.

(Step 2306) Control the “adjust” logic so the transmitter uses a normal(TX) drive-timing-point.

(Step 2307) Control the “adjust” logic so that the “normal path” to thetransmitter is enabled.

(Step 2308) Resume normal transmit and receive operations.

(Step 2309) The received pattern sequence is compared to the expectedpattern sequence from the “pattern” block.

(Step 2310) The calibrate drive-timing-point (TXA/TXB, TX) is adjustedaccording to the results of the comparison.

In the modified sequence, normal transmit and receive operations may berestarted earlier. This is possible because the comparison results aresaved and used to adjust the timing point during the next calibrationprocess.

A more significant saving in overhead is possible in the system of FIG.13 , by changing the order of steps in the process of FIG. 14 , forexample. It is possible to separate the evaluation and update steps aspreviously described. However, it is also possible to perform receiveoperations with the first component while its transmitter is changingthe drive-timing-point between the normal and calibrate values. Theperiodic calibration process could become:

(Step 2401 a) Suspend normal transmit operations, by completingtransactions in progress and preventing new ones from beginning, or byinterrupting transactions that are in progress

(Step 2402 a) Control the “adjust” logic so the transmitter uses acalibrate (TXA/TXB) drive-timing-point according to the stored resultsof the previous comparison.

(Step 2403 a) Control the “adjust” logic that the pattern block iscoupled to the transmitter.

(Step 2404 a) A pattern sequence is created from the “pattern” block andis transmitted onto the interconnect using the selected calibratedrive-timing-point.

(Step 2405 a) The pattern sequence is received in the second componentand placed in storage.

(Step 2406 a) Control the “adjust” logic so the transmitter uses anormal (TX) drive-timing-point.

(Step 2407 a) Control the “adjust” logic so that the “normal path” tothe transmitter is enabled.

(Step 2408 a) Resume normal transmit operations.

Note that receive operations could continue during this process exceptwhen the calibration pattern is actually being transmitted on theinterconnect. In particular, the component could receive while itstransmitter is changing the drive-timing-point between the normal andcalibrate values. The second set of steps for the calibration processwould consist of:

(Step 2401 b) The pattern sequence in storage is transmitted onto theinterconnect by the second component.

(Step 2402 b) The pattern sequence is received using the normal (RX)sample-timing-point.

(Step 2403 b) The received pattern sequence is compared to the expectedpattern sequence from the “pattern” block.

(Step 2404 b) The calibrate drive-timing-point (TXA/TXB, TX) is adjustedaccording to the results of the comparison.

Note that normal transmit and receive operations could continue duringthis process except when the calibration pattern is actually beingreceived from the interconnect.

If reordering and overlapping of calibration steps is done, the overheadof the calibration process can be reduced, improving the effectivesignaling bandwidth of the system and reducing the worst case delay seenby latency-sensitive operations.

The reduction in overhead can also permit the periodic calibrationprocess to be executed at a more frequent rate. The benefit is that thiswill compensate for sources of timing drift that change more rapidly.This will permit more of the bit time to be used for the transmitterdrive time variation and the receiver sampling window, and less of thebit time will be needed for timing drift within the system.

FIG. 25 illustrates an example like that of FIG. 13 , with the exceptionthat the point to point bidirectional link of FIG. 13 is replaced with amultidrop link, coupling component 2500 to a plurality of components2551, 2552. The multidrop link configuration can be applied in otherconfigurations. In the representative example shown in FIG. 25 , a firstbidirectional component 2500 and a plurality of other bidirectionalcomponents 2551, 2552 are connected in a point to multi-pointconfiguration, or multipoint to multipoint configuration, with aninterconnection medium referred to as Link 2502. Normal path 2510 actsas a source of data signals for normal operation of component 2500during transmit operations. Normal path 2531 acts as a destination ofdata signals for component 2500, during normal receive operations. Thecalibration operations are interleaved, and re-ordered, in thisembodiment with normal communications, as described above to improvethroughput and utilization of the communication medium.

The first bidirectional component 2500 includes a block 2505 labeled“pattern”, which can consist of pattern storage or pattern generationcircuitry, and which is used as a source of transmit calibrationpatterns. A multiplexer block 2506 labeled “mux,” implemented forexample using a logical layer or physical layer switch, enables thetransmit calibration pattern set to be driven onto the link by thetransmitter circuit 2503. The transmitter drive point can be adjusted bythe block 2507 labeled “adjust”. In this embodiment, the adjust block2507 includes storage for multiple parameter sets which are applieddepending on the one of the other components 2551, 2552, . . . on thelink to which the transmission is being sent. Component 2500 also hassupport for calibrating receiver 2524, including a block 2528 labeled“pattern”, which can consist of pattern storage or pattern generationcircuitry, and which is used as a source of expected patterns forcomparison with received patterns. A block 2529 labeled “compare”enables the received pattern set to be compared to the expected patternset, and causes an adjustment to be made to either the transmitter orreceiver. The receiver sample point can be adjusted by the block 2532labeled “adjust”. In this embodiment, the adjust block 2507 includesstorage for multiple parameter sets which are applied depending on theone of the other components 2551, 2552, . . . on the link from which thecommunication is being received. In the first component 2500, thecompare block 2529 is used for analysis of both transmit and receivecalibration operations, and is coupled to both the adjust block 2507 forthe transmitter, and adjust block 2532 for the receiver. In the exampleof FIG. 25 , the receiver sample point and transmitter drive point ofthe first bidirectional component 2500 are adjustable. The othercomponents 2551, 2552, . . . are implemented as described with referenceto FIG. 13 without adjustment resources, in this example, and notdescribed here. In alternative embodiments, the components 2551, 2552, .. . on the link may be provided with adjustment and calibrationresources, as described for other embodiments above.

While the present invention is disclosed by reference to the preferredembodiments and examples detailed above, it is to be understood thatthese examples are intended in an illustrative rather than in a limitingsense. It is contemplated that modifications and combinations willreadily occur to those skilled in the art, which modifications andcombinations will be within the spirit of the invention and the scope ofthe following claims.

1. (canceled)
 2. A controller to control a memory component, thecontroller comprising: interface circuitry to receive information fromthe memory component, via at least one link, wherein the interfacecircuitry is to sample the information from the memory componentaccording to edges of a clock signal; and phase adjustment circuitry tovary a phase of the edges of the clock signal; wherein the phaseadjustment circuitry is to establish an operating value of the phaseduring a calibration operation, the operating value to be applied to thesampling of the information, and wherein the phase adjustment circuitryis to from-time-to-time adjust the operating value in response to driftbetween the operating value and a timing point for the sampling of theinformation by the controller, the drift being detected subsequent toestablishment of the operating value.
 3. The controller of claim 2wherein: the memory component is to provide a predetermined data patternto the controller, in connection with the calibration operation; andduring the calibration operation, the interface circuitry is to samplethe predetermined data pattern from the memory component, according torespective phases of the clock signal, and the phase adjustmentcircuitry is to establish the operating value, dependent on one or moreof the respective phases of the clock signal, where the one or morerespective phases of the clock signal each correspond to correct receiptof the predetermined data pattern.
 4. The controller of claim 2 wherein:said controller further comprises circuitry which is to receive apredetermined data pattern from the memory component, in connection withthe calibration operation; during the calibration operation, theinterface circuitry is to receive the predetermined data pattern fromthe memory component multiple times, each of the multiple times suchthat sampling is performed according to a respective phase of the clocksignal; and the phase adjustment circuitry is to establish the operatingvalue according to a phase of the clock signal that corresponds tocorrect sampling of the predetermined data pattern by the controller. 5.The controller of claim 4 wherein: the clock signal is a first clocksignal and the information to be received from the memory device isfirst information; the interface circuitry also comprises a transmitter,wherein the transmitter is to transmit second information to the memorycomponent, according to edges of a second clock signal; the phaseadjustment circuitry is also to vary a phase of the edges of the secondclock signal; and the phase adjustment circuitry is to establish anoperating value of the phase of the edges of the second clock signal,during a calibration operation, the operating value of the phase of theedges of the second clock signal to be applied to the transmission bythe transmitter of the second information, and wherein the phaseadjustment circuitry is to from-time-to-time adjust the operating valueof the phase of the edges of the second clock signal, in response todrift between the operating value of the phase of the edges of thesecond clock signal and a timing point for transmission of the secondinformation.
 6. The controller of claim 5 wherein the at least one linkcomprises a bidirectional link and wherein the transmission ofinformation to the memory component and the receipt of information fromthe memory component each occur over the bidirectional link.
 7. Thecontroller of claim 2 wherein, during the calibration operation: thecontroller is to receive a first calibration pattern from the memorycomponent; the controller is to compare a stored data pattern with thefirst calibration pattern received from the memory component, as-sampledby the interface circuitry; and the phase adjustment circuitry is toestablish the operating value of the phase of the edges of the clocksignal responsive to the comparison between the stored calibration andthe first calibration pattern received from the memory component,as-sampled by the interface circuitry.
 8. The controller of claim 7wherein the first calibration pattern and the stored data pattern areselected by the controller.
 9. The controller of claim 7 wherein theinterface circuitry comprises a transmitter, and wherein the firstcalibration pattern is to be first transmitted by the transmitter to thememory component, and then retransmitted from the memory component backto the controller, in connection with the calibration operation.
 10. Thecontroller of claim 2 wherein, as part of the calibration operation usedto establish the operating value of the phase of the edges of the clocksignal, the phase adjustment circuitry is to identify timing of two dataeye edges associated with correct sampling by the interface circuitry ofthe information from the memory component and is to establish theoperating value of the phase of the edges of the clock signal dependenton a midpoint between the timing of the two data eye edges.
 11. Thecontroller of claim 10 wherein the phase adjustment circuitry, inadjusting the operating value of the phase of the edges of the clocksignal in response to drift, is to, from time-to-time: identify a newvalue for timing for at least one of the two data eye edges; and performthe adjusting of the operating value of the phase of the edges of theclock signal, in dependence on the new value.
 12. The controller ofclaim 2 wherein the interface circuitry further comprises serializationcircuitry, wherein the at least one link comprises a serial transmissionline, and wherein the controller is to, during each calibrationoperation, receive serial data from the memory component via the serialtransmission line.
 13. A method of controlling a memory component, usinga controller, the method comprising: with interface circuitry of thecontroller, receiving information from the memory component, via atleast one link, wherein receiving the information comprises sampling theinformation from the memory component according to edges of a clocksignal; and with phase adjustment circuitry of the controller, varying aphase of the edges of the clock signal; wherein varying the phasecomprises establishing an operating value of the phase during acalibration operation, applying the operating value to the sampling ofthe information and, from-time-to-time, adjusting the operating value inresponse to drift between the operating value and a timing point for thesampling of the information by the controller, the drift being detectedsubsequent to establishment of the operating value.
 14. The method ofclaim 13 wherein: the memory component is to provide a predetermineddata pattern to the controller, in connection with the calibrationoperation; and the method further comprises, during the calibrationoperation, sampling the predetermined data pattern from the memorycomponent, according to respective phases of the clock signal, andestablishing the operating value, dependent on one or more of therespective phases of the clock signal, where the one or more respectivephases of the clock signal each correspond to correct receipt of thepredetermined data pattern.
 15. The method of claim 13 wherein: thecontroller is to receive a predetermined data pattern from the memorycomponent in connection with the calibration operation; and the methodfurther comprises, during the calibration operation, receiving thepredetermined data pattern from the memory component multiple times,each of the multiple times such that sampling is performed according toa respective phase of the clock signal, and establishing the operatingvalue according to a phase of the clock signal that corresponds tocorrect sampling of the predetermined data pattern by the controller.16. The method of claim 15 wherein: the clock signal is a first clocksignal and the information to be received from the memory device isfirst information; the interface circuitry further comprises atransmitter; and the method further comprises with the transmitter,transmitting second information to the memory component, according toedges of a second clock signal, with the phase adjustment circuitry,also varying a phase of the edges of the second clock signal, and withthe phase adjustment circuitry, establishing an operating value of thephase of the edges of the second clock signal, during a calibrationoperation, applying the operating value of the phase of the edges of thesecond clock signal to the transmission by the transmitter of the secondinformation, and, with the phase adjustment circuitry, from-time-to-timeadjusting the operating value of the phase of the edges of the secondclock signal, in response to drift between the operating value of thephase of the edges of the second clock signal and a timing point fortransmission of the second information.
 17. The method of claim 13wherein the method further comprises, during the calibration operation:with the controller, comparing a stored data pattern with a firstcalibration pattern received from the memory component, as-sampled bythe interface circuitry; and with the phase adjustment circuitry,establishing the operating value of the phase of the edges of the clocksignal responsive to the comparison between the stored data pattern andthe first calibration pattern received from the memory component,as-sampled by the interface circuitry.
 18. The method of claim 17wherein the interface circuitry comprises a transmitter, wherein themethod further comprises transmitting, with the memory component, thepredetermined data pattern to the memory component, and wherein thepredetermined data pattern is to then be retransmitted from the memorycomponent back to the controller, in connection with the calibrationoperation.
 19. The method of claim 13 wherein the method furthercomprises, as part of the calibration operation used to establish theoperating value of the phase of the edges of the clock signal, and withthe phase adjustment circuitry: identifying timing of two data eye edgesassociated with correct sampling by the interface circuitry of theinformation from the memory component; and establishing the operatingvalue of the phase of the edges of the clock signal, dependent on amidpoint between the timing of the two data eye edges.
 20. The method ofclaim 19 wherein the method further comprises, with the phase adjustmentcircuitry, and from time-to-time: identifying a new value associatedwith the timing of at least one of the two data eye edges; andperforming the adjusting of the operating value of the phase of theedges of the clock signal, in dependence on the new value.
 21. Acontroller comprising: means for receiving information from a memorycomponent, via at least one link, wherein the means for receiving is tosample the information from the memory component according to edges of aclock signal; and means for varying a phase of the edges of the clocksignal; wherein means for varying is to establish an operating value ofthe phase during a calibration operation, is to apply the operatingvalue to the sampling of the information and, from-time-to-time, is toadjust the operating value in response to drift between the operatingvalue and a timing point for the sampling of the information by thecontroller, the drift being detected subsequent to establishment of theoperating value.